Modern computer systems are capable of very high performance. Power consumption generally increases with increased performance. Often, less than maximum performance is adequate for a particular use or computer application, though many computer systems still unnecessarily operate at higher performance levels, thus wasting power and reducing battery life of portable devices. Ideally, the computer system's performance would be adjusted to meet the application's need while minimizing power usage.
FIG. 1 shows an example of a system in which a central clock integrated circuit (IC) or chip 20 generates one or more clock signals, each of which is supplied to a corresponding system component 100(1) to 100(N). Examples of system components are a processor, memory controller and PCI bus controller. Each system component 100(1) to 100(N) may have its own clock processing circuit 110(1) to 110(N) that is a consumer or user of a clock signal supplied by the central clock chip 20. Examples of clock processing circuits are phase lock loop circuits (PLL) and delay locked loop circuits (DLLs). A clock processing circuit may increase, decrease or maintain the same the frequency of the clock signal supplied to it by the central clock chip 20, depending on the particular system component. For purposes of clarity, a clock signal supplied to a clock processing circuit 110(1) to 110(N) from the central clock chip 20 is called a central clock signal. The central clock chip 20 may generate several central clock signals. The clock signal that is generated by the clock processing circuit in a system component is called a processed clock signal. The other elements in a system component operate on the processed clock signal(s) generated by the clock processing circuit contained therein.
Techniques exist to reduce computer system performance when the processing demands are low. Reducing computer system performance is usually done by reducing the frequency of the processed clock signal internally used by various system components, such as the processor, memory and busses because these components consume power on every clock cycle. For example, as shown in FIG. 2, the processed clock signal for a processor is reduced when the operating system enters an idle state. Ideally, the frequency during the idle state would be as low as possible and switching between frequencies would be instantaneous. When interrupts or signals occur, demanding the processor's attention, the frequency of the processed clock signal for the processor is returned to the maximum or some desired frequency. The power a computer system saves depends on the time duration of reduced performance (at the lower clock frequency) and how much the performance has been reduced, i.e., how low the processed clock frequency is made.
Computer systems have complex clocking systems, typically with a central clock chip driving many system components as shown in FIG. 1. The clock processing circuit in some system components, such as a processor, is a PLL that converts (multiplies) a central clock signal to a higher frequency. A multiplying PLL introduces limits on the range of frequencies the PLL can achieve and how quickly it can transition from one frequency to another. This is due in part to filter circuits in the PLL that limit the rate of change and may introduce instability when changing frequencies rapidly. A common problem with PLLs is called overshoot (or undershoot), where a PLL may as a consequence of a frequency change, generate a frequency higher (or lower) than the system maximum, causing system failures. FIG. 3 illustrates the overshoot problem. To avoid this problem, computer systems are designed to limit the rate of frequency change. This leads to an unfortunate tradeoff: slow response from the system when returning to full speed versus limiting the amount of frequency reduction and thus reducing power savings.
A better solution is to adjust for the characteristics of the clock processing circuit (e.g., PLL, DLL, etc.) when changing the frequency of the central clock signal to achieve the fastest possible frequency transitions for the processed clock signal. Faster transitions mean that, for a given response time, the power savings associated with operation at a lower frequency can be maximized.